Gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) is currently the technology of choice for radio frequency (RF) power amplifier (PA) due to its excellent RF performance. PA is one of the most energy consuming devices in RF front-end modules, and demands high efficiency. The push-pull (PP) configuration, whereby two transistors amplify alternative half cycles of the RF signal, is a basic building block for high efficiency applications. However, the NPN-PNP complementary GaAs HBT PP configuration is rarely employed in PA design. On a same GaAs substrate, the collector currents of the PNP and NPN HBTs are largely different due to the optimum current density differences. And it limited the power handling capability of the circuit. The PNP and NPN HBTs are rarely fabricated on the same chip for the great difference requirement in the epitaxial layer to achieve excellent performance. And it’s complex and expensive to fabricate on the same substrate. In the conventional non-complementary PP configuration, an input anti-phase splitter and output anti-phase combiner are usually required. These are often based on transformers or passive baluns. Both can be physically large, making them unsuitable for miniaturization or IC fabrication.
First, a high efficiency N-type non-complementary PP PA based on GaAs HBT with single ended input and output (I/O) ports is studied. Then, based on the above study, a broadband differential-push-pull (DPP) PA with high efficiency and linearity is investigated, including the differential configuration, thermal distribution optimization technique, adaptive linearization bias technique, broadband matching technique and circuit implement methdology. Several creative works have been done in this dissertation:
(1) Based on N-type GaAs HBT process and the inverted nature of the collector and emitter output signals of HBT, a non-complementary PP PA with single ended I/O ports and high efficiency is proposed. There are no needs of baluns at I/O port. The simulation results show that 32dBm P1dB (output power at 1dB compression point), 21dB power gain and 50% PAE (power added efficiency) are achieved at 2.1GHz. In addition, the second and third harmonic component of the proposed PA reduces 4.04dB and 9.19dB, respectively, compared with the traditional common emitter PA in the case of same level of Pout.
(2) Based on the configuration of differential structure and two same PP stages, a DPP PA with high linearity is proposed to improve the swing and the symmetry of the output waveform of the non-complementary PP PA. To save the area of the layout, the input stage employs an active HBT instead of the passive balun. The simulation results show that, with the operating frequency of 1.8GHz to 2.4GHz, the differences between peak values of the positive and negative half cycle of the output are 1.02V and 1.49V, respectively, for the proposed DPP PA and the PP PA when working at 2.1GHz. The difference values account for 5.09% and 15.38% of the output voltage swing, respectively, with an improvement of 10.29%.
(3) A novel type of thermal shunt structure in layout design is proposed to optimize the thermal distribution and improve PAE of PA. The proposed thermal shunt structure introduces collector metal to provide a new heat dissipation path from the power cells of the chip to the ground. It is specially designed to improve the thermal distribution of the base-collector (BC) junction. The simulation results show that, by adding this cooling path, the maximum temperature of the power cells is effectively reduced from 163°C to 148°C when the circuit is working normally, with an improvement of 9.2%. And the PAE is enhanced by 2%.
(4) Based on the above methodologies and techniques, a 1.5GHz -2.7GHz DPP PA is implemented using 2μm N-type GaAs HBT process with broadband, high efficiency and linearity. The gain is improved by 1dB based on adaptive linearization bias technique. The bandwidth is expanded to 1.2GHz based on patered travelling wave input matching technique. The difference between peak values of output is improved by 10.45% based on the DPP strcture. The chip size is 0.9×1.5mm2. An off-chip transmission line Balun is used to combine the output signals of the two push-pull stages for measurment. The measurement results show the input return loss is better than 15dB from 1.78GHz to 2.67GHz. 34dBm P1dB, 27dB power gain and 45% PAE are achieved at 2.1GHz.
Consequently, based on above works of this dissertation, high efficiency, high linearity and high power in 1.5GHz-2.7GHz broad operation frequcncy for DPP PA is realized. The proposed broadband PA can be applied in Beidou satellite, LTE and WLAN communication systems.