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类型 应用研究 预答辩日期 2017-11-08
开始(开题)日期 2014-12-15 论文结束日期 2017-07-28
地点 李文正楼射光所会议室 论文选题来源 学校自选项目    论文字数 5.5 (万字)
题目 100G以太网物理层研究及关键模块ASIC实现
主题词 物理编码子层(PCS),64B/66B编码器(64B/66B Encoder),扰码器(Scrambler),多通道分发(MLD),变速箱(Gearbox)
摘要 以太网以其成本低、可靠性高、安装维护简单等优点而成为普遍采用的网络技术。随着互联网技术的不断发展和用户数量的不断增加,用户对数据传输和接入带宽的需求将越来越大。在2010年制定了40G/100G以太网的标准IEEE802.3ba。 据统计,在计算领域,带宽能力每24个月翻一倍,而网络带宽则每18个月翻一倍,平均下来,到2015年网络必须支持1TB每秒的能力,到2020年必须支持10TB每秒的能力,这一数字几乎是2010年的100倍。为了满足这样的带宽需求,以太网必须向更高速度进发,400GE正是下一站目标。400GE标准命名为IEEE802.3bs,最晚2017年发布。本文对100G以太网物理层进行研究,并严格按照IEEE802.3ba和IEEE802.3bmTM/D1.1标准,设计了一个电气接口为4×25Gbps的100G以太网物理编码子层(PCS)架构,对PCS中的64B/66B编码器,扰码器,多通道分发模块和变速箱等关键模块进行了研究,并且设计了一个基于全数字锁相环频率合成器来产生PCS各模块的时钟。主要内容如下: 1)按照IEEE802.3ba和IEEE802.3bmTM/D1.1标准,设计了一个电气接口为4×25Gbps的100G以太网物理编码层(PCS)架构, 并采用半定制对该PCS发送端电路进行了ASIC设计,该PCS主要由四个功能模块组成,分别是64B/66B编码器,扰码器,多通道分发模块和变速箱。 2)64B/66B编码器设计:采用流水线结构设计了一个64B/66B编码器,并且为了便于测试,在编码器的前级设计了一个伪随机码发生器,不间断产生控制码和数据码。 3)扰码器设计:设计了一个256位并行扰码器,采用二级流水线结构,大大提高了模块电路的运行速度。 4)多通道分发模块(MLD)设计:基于IEEE802.3 ba标准,把输入的数据轮循分发为20路。首先,针对高速的数据流,对数据进行多通道的分发,可以降低对时钟频率的要求,以满足实际逻辑器件的设计;其次,MLD机制中虚通道的通道数L如满足L=LMC(M,N),则可适配多种不同的光模块器件;最后,在虚通道中添加对齐字,进行虚通道对齐,可以消除通道延时,实现数据正确恢复的作用。 5)变速箱设计:提出了一种基于轮循存储方式的寄存器结构变速箱,由于采用这种特别的存储方式使它可以在一段时间范围内开始输出,而不只限于某一时间点才能输出,因此可以克服输入输出时钟相位差的影响,大大地提高电路的速度和稳定性。再经过结构的优化及采用流水线结构的设计,最后该变速箱的时钟速度超过700 MHz。 6)全数字锁相环(ADPLL)设计:设计了一个参考时钟为390.625MHz,输出时钟频率分别78.125MHz、644.53125MHz和2.578125GHz的PCS时钟电路,主体结构为ADPLL。
英文题目 100G ETHERNET PHYSICAL LAYER RESEARCH AND KEY MODULES ASIC IMPLEMENTATION
英文主题词 Physical Code Sublayer(PCS),64B/66B Encoder,Scrambler,Multilane Distribution(MLD),Gearbox
英文摘要 Ethernet is widely used because of its low cost, high reliability, simple installation and maintenance. With the continuous development of Internet technology and the increasing number of users, the demand for data transmission and access bandwidth will become larger and larger. In 2010 to develop a standard 40G/100G Ethernet IEEE802.3ba. According to statistics, in the field of computing the bandwidth capacity doubles every 24 months, while the network bandwidth will double every 18 months, on average, to 2015 network must support 1TB per second, the ability to 2020 must support 10TB per second, the figure is almost 100 times that of 2010. In order to meet the bandwidth requirements, Ethernet must move towards a higher speed, 400GE is the next target. 400GE standard named IEEE802.3bs, the latest release in 2017. This paper focuses on the research of 100G Ethernet physical layer, and in strict accordance with the IEEE802.3ba and IEEE802.3bmTM/D1.1 standard, design an electrical interface of 4 × 25Gbps 100G Ethernet physical layer encoding (PCS) architecture, and research the key modules of the PCS circuit, that is, 64B/66B encoder, scrambler, multi-channel distribution module and gearbox。In addition, in order to solve the problem of multiple clock sources in the PCS circuit, an all digital phase-locked loop(ADPLL) is designed. The main contents are as follows: 1)according to IEEE802.3ba and IEEE802.3bm TM/D1.1standard, an electrical interface of 4 × 25Gbps 100G Ethernet physical layer encoding (PCS) architectureis designed, it is finishedASIC design and taped out in semi-custom. the PCS circuit is mainly composed of four functional modules, namely 64B/66B encoder, scrambler, multi-channel distribution module and gearbox. 2)64B/66B encoder design: a pipelined 64B/66B encoderis designed.In order to easy tohardware test, at the previous stage of the encoder, a pseudo-random code generatoris added to generate control codes and data codes consecutively. 3)Scrambler design: a 256-bit parallel scrambler design, with two stage pipeline structure, greatly improves the speed of it. 4)Multi channel distribution module (MLD) design: Based on the IEEE802.3ba standard, the input data is round distributedas 20 lanes. First of all, according to the high-speed data stream, multi-channel distribution of data, can reduce the clock frequency to meet the design requirements of the actual logic device; secondly, the number of channels of virtual channelL inMLD mechanism, if L=LMC (M, N) is met, it can be adapted to a variety of optical devices with different modules; finally, for the virtual channel alignment,the word aligned blocks areaddedin the virtual channel, it can eliminate channel delay, achieve the correct data recovery function. 5)Gearbox design: a round robin storage mode register structure based 66:8 gearbox is designed, so that it can start to output in a certain period of time, rather than only one time pointby the special storage mode, so it can overcome the influence of input clock phase, greatly to improve the speed and stability of circuit. After the optimization of the structure and the design of the structure of the pipeline, the clock speed of more than 700 MHz. 6)All digital phase-locked loop (ADPLL) design: the clock circuit of the PCS is designed, its’reference clock is390.625MHz, and can produce 78.125MHz, 644.53125MHz and 2.578125GHz output clock frequency.Its’ main part is ADPLL.
学术讨论
主办单位时间地点报告人报告主题
东南大学射光所 2013.07 江宁无线谷A4-4212 阮伟华 100GE PHY设计
东南大学射光所 2014.10 江宁无线谷A4-4212 阮伟华 100G/s 以太网PCS层发送端芯片设计
东南大学射光所 2015.06 江宁无线谷A4-4212 阮伟华 100G以太网PCS接收电路设计
东南大学射光所 2015.11 江宁无线谷A4-4212 阮伟华 5.2G半速率ADPLL电路设计
     
学术会议
会议名称时间地点本人报告本人报告题目
ICNCDP2013 2013.09 山东济南 A kind of logarithmic function hardware encryptor and decryptor
2015ICoICT 2015.05 印尼巴厘岛 A High-Speed Gearbox Based on Phase Independent Architecture for 100G Ethernet Physical Coding Sublayer
     
代表作
论文名称
A 14.5Gb/s Word Alignment Circuit in 0.18μm CMOS Technology for high-speed SerDes
A High-Speed Gearbox Based on Phase Independent Architecture for 100G Ethernet Physical Coding Subla
A 0.18?um CMOS Transmit Physical Coding Sublayer IC for 100G Ethernet
High speed and reliability gearbox for 100GE physical coding sublayer
 
答辩委员会组成信息
姓名职称导师类别工作单位是否主席备注
刘陈 正高 教授 博导 南京邮电大学
乔庐峰 正高 教授 博导 解放军理工大学
王志功 正高 教授 博导 东南大学
冯军 正高 教授 博导 东南大学
樊祥宁 正高 教授 博导 东南大学
      
答辩秘书信息
姓名职称工作单位备注
唐路 副高 副教授 东南大学