Ethernet is widely used because of its low cost, high reliability, simple installation and maintenance. With the continuous development of Internet technology and the increasing number of users, the demand for data transmission and access bandwidth will become larger and larger. In 2010 to develop a standard 40G/100G Ethernet IEEE802.3ba.
According to statistics, in the field of computing the bandwidth capacity doubles every 24 months, while the network bandwidth will double every 18 months, on average, to 2015 network must support 1TB per second, the ability to 2020 must support 10TB per second, the figure is almost 100 times that of 2010. In order to meet the bandwidth requirements, Ethernet must move towards a higher speed, 400GE is the next target. 400GE standard named IEEE802.3bs, the latest release in 2017. This paper focuses on the research of 100G Ethernet physical layer, and in strict accordance with the IEEE802.3ba and IEEE802.3bmTM/D1.1 standard, design an electrical interface of 4 × 25Gbps 100G Ethernet physical layer encoding (PCS) architecture, and research the key modules of the PCS circuit, that is, 64B/66B encoder, scrambler, multi-channel distribution module and gearbox。In addition, in order to solve the problem of multiple clock sources in the PCS circuit, an all digital phase-locked loop(ADPLL) is designed. The main contents are as follows:
1）according to IEEE802.3ba and IEEE802.3bm TM/D1.1standard, an electrical interface of 4 × 25Gbps 100G Ethernet physical layer encoding (PCS) architectureis designed, it is finishedASIC design and taped out in semi-custom. the PCS circuit is mainly composed of four functional modules, namely 64B/66B encoder, scrambler, multi-channel distribution module and gearbox.
2）64B/66B encoder design: a pipelined 64B/66B encoderis designed.In order to easy tohardware test, at the previous stage of the encoder, a pseudo-random code generatoris added to generate control codes and data codes consecutively.
3）Scrambler design: a 256-bit parallel scrambler design, with two stage pipeline structure, greatly improves the speed of it.
4）Multi channel distribution module (MLD) design: Based on the IEEE802.3ba standard, the input data is round distributedas 20 lanes. First of all, according to the high-speed data stream, multi-channel distribution of data, can reduce the clock frequency to meet the design requirements of the actual logic device; secondly, the number of channels of virtual channelL inMLD mechanism, if L=LMC (M, N) is met,
it can be adapted to a variety of optical devices with different modules; finally, for the virtual channel alignment,the word aligned blocks areaddedin the virtual channel, it can eliminate channel delay, achieve the correct data recovery function.
5）Gearbox design: a round robin storage mode register structure based 66:8 gearbox is designed, so that it can start to output in a certain period of time, rather than only one time pointby the special storage mode, so it can overcome the influence of input clock phase, greatly to improve the speed and stability of circuit. After the optimization of the structure and the design of the structure of the pipeline, the clock speed of more than 700 MHz.
6）All digital phase-locked loop (ADPLL) design: the clock circuit of the PCS is designed, its’reference clock is390.625MHz, and can produce 78.125MHz, 644.53125MHz and 2.578125GHz output clock frequency.Its’ main part is ADPLL.