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类型 综合研究 预答辩日期 2018-04-04
开始(开题)日期 2014-05-23 论文结束日期 2018-01-07
地点 ASIC工程中心4楼会议室 论文选题来源 学校自选项目    论文字数 8 (万字)
题目 锁相环电路的可测性设计研究
主题词 电荷泵锁相环,可测性设计,故障检测,抖动测量,时间数字转换器
摘要 锁相环广泛应用于频率合成、时钟分配、相位解调以及时钟恢复等,是无线通信、光纤链路、射频收发机及微型计算机等必不可少的一部分,其可测性设计对于确保整个电子系统的性能具有重要意义。常规锁相环可测性方法将结构测试和性能测试分离,导致测试需要复杂的外部测试仪器来验证待测锁相环的性能,或者不能检测锁相环中是否存在故障;且测试电路较为复杂,面积开销大。将两者分离测试需要较高的测试成本和较长的测试时间,降低了测试技术工程应用的价值。而当前少数几种能够同时完成结构测试和性能评估的锁相环可测性方法大多采用相互独立的测试结构,致使测试电路更加复杂,面积开销甚至可能超过待测锁相环电路的芯片面积,成本较高,且其故障覆盖率和测试分辨率仍有待提高。因此本文从兼顾结构测试和性能评估的锁相环可测性方案出发,重点研究了用同一个具有较高故障覆盖率和抖动测量分辨率的可测性电路同时完成锁相环的片上故障检测和抖动测量。 本文的主要工作及创新点包括:(1) 研究了电荷泵锁相环结构中故障与抖动的关系,分别从系统理论模型,行为级模型和晶体管级模型入手,定性定量分析了故障对抖动的影响。(2) 提出了一种兼顾结构测试和性能评估的锁相环可测性结构。该结构提出一种高分辨率的时间数字转换器(TDC)结构用于同时实现锁相环的片上抖动测量和故障检测,其中使用待测锁相环作为延时探测器,探测时间差的范围更广;使用一个信号处理单元自动完成锁相环故障检测模式,抖动测量模式和时钟产生模式的相互转换,测试流程更简单;且只需一个外部使能信号用于测试,最小化对外部测试资源的需求。经验证,该结构对待测锁相环的性能影响较小,且具有较高的故障覆盖率和测量分辨率。 (3) 提出了基于缺陷测试 (DOT) 的全数字锁相环片上故障测试结构。该结构使用了一个新的鉴频鉴相器结构用于片上产生测试信号并控制整个检测流程,同时结合待测锁相环中存在的大部分模块作为输入激励产生器和用于测试评估的故障特征提取装置来完成故障检测,降低了测试面积开销。该结构只对待测锁相环的数字部分进行更改,因此对待测锁相环的性能影响较小。附加的测试电路是全数字并且极易实现,经优化整个测试电路最终由14个D触发器和3个多路复用器组成。经验证,该结构的故障覆盖率可达到98.75%。(4) 提出了基于TDC的全数字锁相环片上抖动测量结构。该结构使用了一个新型TDC结构用于锁相环的片上抖动测量,大大降低了测试面积开销。应用所设计的鉴频鉴相器结构探测时间差,使得该电路尤其适用于探测极小或极大的时间抖动。而所提出的自参考测试电路避免了片上抖动测量时对外部无抖动参考信号的需求,降低了测试成本。测试电路只对待测锁相环的数字部分进行微小更改,因此对待测锁相环的性能影响较小。经验证,该结构的抖动测量分辨率能达到0.78ps,测量误差为5.78%。 本文在TSMC 0.13-μm CMOS工艺上实现了该兼顾结构测试和性能评估的锁相环可测性结构,芯片面积是575.7 × 582.8 μm2,其中额外添加的可测性设计电路占0.78%。故障覆盖率为98.33%。抖动测量分辨率为0.9865ps,测量误差为11.91%,待测锁相环的均方根抖动为17.25ps。结果表明了所提出的锁相环可测性结构的有效性,实现了较高的故障覆盖率和抖动测量分辨率,并大大降低了面积开销。
英文题目 Research of design-for-test of phase-locked loops circuits
英文主题词 charge pump phase-locked loop, design-for-test, fault detection, jitter measurement, time-to-digital converter
英文摘要 The phase-locked loop (PLL) is widely used in a large number of applications such as frequency synthesis, phase demodulation, clock distribution and timing recovery. It is essential for systems like wireless phones, optical fiber links and micro-computers. Thus, the design-for-test (DFT) of PLLs is of great significance to ensure the performance of the entire electronic system. The conventional PLL testability method which separates the structural test and performance verification, leads to the need of complex external test instruments to verify the performance of PLL under test, or it cannot check the structure fault in PLL circuits. And the test circuit is complex. The area overhead is large. Both the DFT technologies need high test cost and long test time, which reduce its value for engineering application. There are a few kinds of design-for-test methods which can complete both structure testing and performance evaluation, but most of them use independent test structure. Thus the test circuit is more complex. The test area overhead may larger than chip area of the PLL. Its fault coverage and resolution of jitter measurement is also need to be improved. Therefore, based on the PLL DFT scheme considering structural test and performance evaluation, we mainly focus on the research of fault detection and jitter measurement on-chip using a same DFT circuit with high fault coverage and jitter measurement resolution. The main works of this thesis are as follows: (1) The relationship between structure fault and jitter of CP-PLL is studied. Based on the system theory model analysis, the behavioral model and the transistor level model, the impact of structure fault on jitter of CP-PLL is qualitatively and quantitatively analyzed. (2)System design and verification of a low cost DFT structure of CP-PLL which provides both the fault detected and timing jitter measured. A time-to-digital converter (TDC) with high resolution is proposed in the DFT structure for achieving fault detection and jitter measurement of PLL on-chip. In which it uses the PLL under test as the time difference detector, thus the detection range is very wide. A signal processing unit is also employed for automatically transforming mode among the fault detection, jitter measurement and clock generation. Thus the testing process is very simple. And only one external signal is used to enable the test, which minimize the demand for external test resources. It is verified that the structure has little influence on the performance of the PLL, and it has high fault coverage and measurement resolution. (3) Design and verification of an all digital fault detection methodology based on defect-oriented-test (DOT). It proposes a new simple PFD structure to generate test signals on chip and control the whole detection process. Combined with the most existing blocks in CP-PLL as the input stimulus generator and fault feature extracted devices for testing evaluation, the area overhead is reduced. With a little modification on the digital part of the CP-PLL, it has a little influence on the performance. The additional test structure is all digital and easily implemented with 14 DFFs and 3 MUXs. It is verified that the fault coverage of the structure can reach 98.75%. (4) Design and verification of an all digital jitter measurement methodology based on TDC. In the structure, by proposed a new TDC structure for on-chip jitter measurement of CP-PLL, it achieves a small test area overhead. By employed a new PFD structure to detect the time difference, it is more suitable for detecting a timing jitter which is extremely small or big. Used the proposed self-referred circuit, it does not need an additional jitter-free reference signal for on-chip jitter measurement. Thus it reduces the test cost. The proposed DFT structure only has a minor modification on the digital part of the CP-PLL, thus it has a little adverse influence on the circuit performance. It is verified that it can detect a timing jitter of 0.78ps with a measurement error of 5.78% The DFT structure of PLL is built on the TSMC 0.13-μm CMOS technology.The chip area is 575.7 × 582.8 μm2, in which the additional test circuit accounts for 0.78%.The fault coverage is 98.33%. The RMS jitter of CP-PLL is 17.25ps. Compared to the results of test equipments, the proposed DFT structure gets a relatively high resolution of 0.9865ps with a measurement error of 11.91%. Results demonstrate that the effectiveness of the proposed DFT structure of PLL with high fault coverage and jitter measurement resolution. It greatly reduces the test area overhead.
学术讨论
主办单位时间地点报告人报告主题
东南大学ASIC中心 2017.06.27 逸夫科技馆401 閤兰花 锁相环电路的可测性研究
东南大学ASIC中心 2013.04.11 逸夫科技馆401 閤兰花 模拟电路内建自测试方法研究
东南大学ASIC中心 2013.10.23 逸夫科技馆407 蔡志匡 锁相环内建自测试研究
东南大学ASIC中心 2014.03.26 逸夫科技馆401 陈超 Introduction of Cadence and Hspice
东南大学ASIC中心 2014.09.30 逸夫科技馆407 閤兰花 PLL/ADC的内建自测试
东南大学ASIC中心 2015.06.02 逸夫科技馆407 閤兰花 锁相环测试方法
The University of Texas at Austin 2015.12.21 Computer Engineering Center 閤兰花 Design for Testability & Built-In Self-Test
The University of Texas at Austin 2016.05.23 Computer Engineering Center Joon-Sung Yang VLSI TEST:BIST Design
     
学术会议
会议名称时间地点本人报告本人报告题目
IEEE 8th International Symposium on Intelligent Signal Processing 2013.09.16– 2013.09.18 葡萄牙 An All-Digital Built-In Self-Test for Charge-Pump Phase-Locked Loops
The 20th Asia-Pacific Conference on Communications 2014.10.01– 2014.10.03 泰国 A Methodology of Fault Detection using Design for Testability of CP-PLL
     
代表作
论文名称
A low-cost built-in self-test for CP-PLL based on TDC
an all-digital built-in self-test for charge-pump phase-locked loops
A Methodology of Fault Detection using Design for Testability of CP-PLL
Built-in self-test structure for fault detection of charge-pump phase-locked loop
 
答辩委员会组成信息
姓名职称导师类别工作单位是否主席备注
陈军宁 正高 教授 博导 安徽大学 主任委员
吴宁 正高 教授 博导 南京航空航天大学
廖小平 正高 教授 博导 东南大学
陆生礼 正高 研究员 博导 东南大学
张萌 副高 副教授 博导 东南大学
      
答辩秘书信息
姓名职称工作单位备注
李红 其他 讲师 东南大学 秘书