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类型 基础研究 预答辩日期 2018-02-02
开始(开题)日期 2015-06-15 论文结束日期 2017-12-04
地点 李文正楼北412 论文选题来源 973、863项目     论文字数 6.5 (万字)
题目 40 Gb/s 光纤通信光接收机跨阻放大器研究与实现
主题词 光接收机,跨阻放大器,低噪声,高线性度,宽带电路
摘要 随着互联网的发展,网络的创新性应用扩展到生活的各个方面,数据流量不断增大,对网速要求越来越高。为了突破半导体器件自身带宽、功耗的限制,高阶调制技术良好的频谱利用效率成为400 Gb/s 光纤通信标准的潜在应用方案。高阶调制格式决定了通信信号多电平的特性,从而要求光纤通信模拟前端电路同时具备低噪声、高线性度和宽带的特性。 本文针对高阶调制格式的光纤通信系统的应用要求,对光接收机中低噪声、高线性度和宽带的跨阻放大器展开研究。首先对晶体管的噪声模型进行分析,研究单端输入和差分输入跨阻放大器的噪声模型;接着根据二阶系统的频率响应特性,研究了跨阻放大器的等效输入噪声的计算方法;继而根据BJT 的Kirk 效应,结合电流密度与温差的关系,提出了计算BJT 器件低噪声优化偏置电流密度的方法;之后对BJT 跨阻放大器的高频噪声转角频率进行了详细研究,并得出BJT 跨阻放大器的高频噪声转角频率计算公式;综合上述研究成果,提出了宽带,高线性度和低噪声跨阻放大器优化设计流程。 理想的全对称跨阻放大器具有处理差分输入信号的能力,并能够抑制偶次谐波和共模噪声,从而具有良好的线性度,是高线性度模拟接收前端放大器的理想选择。本文首先设计了40 Gb/s 低噪声全对称TIA。全对称跨阻放大器需要自零反馈环路保证其良好的均衡性,才能抑制偶次谐波和共模噪声。传统自零反馈环路在前置跨阻放大器的输入端会引入额外的噪声,本文在此基础上利用Cascode 放大器设计出低噪声全对称TIA 的全对称输入级,提出一种自零反馈环路,在保证全对称跨阻放大器拥有良好均衡性的同时,避免在全对称跨阻放大器的输入端引入额外噪声。为构成完整的低噪声全对称TIA,设计了电压放大级与输出缓冲级,并推导出射极退化电阻放大器线性输入范围计算公式。本文设计的40 Gb/s 低噪声全对称TIA 采用Gloubal Foundries (GF)8HP 0.13 um SiGe BiCMOS 工艺实现,芯片测试结果显示其等效输入噪声电流功率谱密度为9.6 pA/√Hz、-3dB带宽为32 GHz、差分跨阻增益为2704 Ω 和117 mW的整体功耗。 在分析Cascode 全对称跨阻放大器缺点的基础上,本文采用Regulated Casocde 结构设计了40Gb/s 高线性度全对称TIA。为保证高线性度全对TIA 的高动态线性输入范围,通过借鉴、优化低噪声全对称TIA 的自零反馈环路,使得高线性度全对称TIA 的自零反馈环路同时获得了过载补偿的功能。最后利用低噪声全对称TIA 的电压放大器与输出缓冲级,构成了完整的高线性全对称TIA。本文的40 Gb/s 高线性度全对称TIA 同样采用GF 8HP 工艺实现,芯片测试结果显示其等效输入噪声电流功率谱密度为10 pA/√Hz、-3dB 带宽为28 GHz、差分跨阻增益为2239 Ω 和95 mW 的整体功耗。40 Gb/s 高线性度全对称TIA 在0.1 mA 静态输入电流、总谐波失真小于5% 的情况下,动态差分输入电流范围最高达2.6 mApp。 单端输入跨阻放大器相比差分输入结构,功耗更低,结构更简单,寄生电容更小,相对容易实现更大的带宽。为了与全对称结构跨阻放大器进行对比,在研究全对称跨阻放大器的基础上,本文设计了一种40 Gb/s 全新结构单端输入TIA。同样采用GF 8HP 工艺,芯片测试结果显示其等效输入噪声电流功率谱密度为16.7 pA/√Hz、-3dB 带宽为35 GHz、跨阻增益为1580 Ω 和88 mW 的整体功耗。 综合上述三款芯片的后仿真与测试结果,三种跨阻放大器都具有较好的性能,分别实现了显著的低噪声,高线性度和宽带的性能。能同时满足非归零码和高阶调制光纤通信系统的应用要求。目前国内在低噪声、高线性度和宽频跨阻放大器设计方面与国际上仍有一定差距,本文工作不仅能够推动相关领域进一步向前发展,具有重要的学术价值,而且对高性能模拟集成电路的设计具有重要应用价值。
英文题目 RESEARCH AND REALIZATION ON 40 GB/S TRANSIMPEDANCE AMPLIFIER FOR OPTICAL RECEIVERS
英文主题词 Optical Receiver, Transimpedance Amplifier, Low Noise, High Linearity, Broadband Circuit
英文摘要 With the development of the Internet, the network of innovative applications extended to all aspects of life, followed by data traffic continues to increase, while the speed requirements are getting higher and higher. In order to break through the bandwidth of the semiconductor device itself and the power consumption limit, the high-order modulation technology has good spectrum utilization efficiency as the potential application scheme of 400 Gb/s optical fiber communication standard. The high-order modulation scheme determines the characteristics of the multi-level communication signal, which requires optical fiber communication analog front-end circuit with both broadband, high linearity and low noise. This paper is for high-order modulation format optical fiber communication system application requirements, the optical receiver in the broadband, high linearity and low noise transimpedance amplifier to start research. Firstly, the noise model of the transistor is analyzed, and the noise model of the single-ended input and the differential input transimpedance amplifier is studied. Then, according to the frequency response characteristic of the second order system, the equivalent input noise of the transimpedance amplifier is studied. Basing on BJT’s Kirk effect combined with the relationship between the current density and the temperature difference, the method of calculating the low-noise optimized bias current density of the BJT device is proposed. The formula to calculate the high frequency noise corner of the BJT transimpedance amplifier is derived in detail. Finally, the optimization design flow of broadband, high linearity and low noise transimpedance amplifier is proposed based on synthesizing the conclusions in this work. An ideal fully symmetrical transimpedance amplifier with the ability to handle differential input signals, and to suppress even harmonics and common mode noise, resulting in good linearity, is ideal for high linearity analog receive front-end amplifiers. The design of the 40 Gb/s low-noise fully-symmetric TIA is completed firstly in this work. However, a fully symmetrical transimpedance amplifier needs an auto-zero feedback loop to ensure its quality balance operation, in order to suppress even harmonics and common-mode noise. The conventional auto-zero feedback loop introduces extra noise at the input of the pre-transimpedance amplifier. Based on this, a cascode amplifier is used to design a fully symmetrical input stage of the low-noise fully-symmetric TIA, and a auto-zero feedback loop is created to ensure that the symmetrical transimpedance amplifier has a good balance operation, while avoiding the introduction of excess noise at the input of the fully symmetrical transimpedance amplifier. In order to form a complete low noise symmetrical TIA, a voltage amplifier stage and an output buffer stage are designed, and a formula for calculating the linear input range of the emitter degenerative resistor amplifier is deduced. The low-noise fully symmetric TIA is implemented using the Gloubal Foundries (GF) 8HP 0.13 m SiGe BiCMOS process. The chip test results show that the equivalent input noise current power spectral density is 9.6 pA/√Hz, -3dB bandwidth of 32 GHz, 2704 Ω differential transimpedance gain and 117 mW overall power consumption. Based on the analysis of the shortcomings of the cascode symmetric transimpedance amplifiers, the 40 Gb/s high-linearity fully-symmetric TIA is designed with regulated casocde amplifier. In order to ensure a high dynamic linear input range of the high linearity symmetric TIA, the self-zero feedback loops of the high linearity symmetry TIA achieves simultaneously the function of overload compensation by drawing on and optimizing the self-zero feedback loop of the low-noise fully symmetrical TIA. Finally, the use of low-noise fully symmetrical TIA voltage amplifier and output buffer stage, constitute a complete high-linear fully symmetry TIA. The high-linearity fully-symmetry TIA in this paper is implemented using the GF 8HP process, and the chip test results show that the equivalent input noise current power spectral density is 10 pA/√Hz , -3dB bandwidth of 28 GHz, 2239 Ω differential transimpedance gain and 95 mW overall power consumption. The post-simulation indicates that the high-linearity fully symmetric TIA has a differential input current range of up to 2.6 mApp at 0.1 mA quiescent input current with less than 5% total harmonic distortion. Single-ended input transimpedance amplifier compared to the differential input structure, lower power consumption, simpler structure, smaller parasitic capacitance, relatively easy to achieve greater bandwidth. In order to compare with a full-symmetrical structure transimpedance amplifier, and based on the study of a full-symmetric transimpedance amplifier, a novel structure of 40 Gb/s single-ended input TIA is designed. The same results were obtained using the GF 8HP process. The chip test results show that the equivalent input noise current power spectral density is 16.7 pA/ √Hz, -3dB bandwidth of 35 GHz, 1580 Ω transimpedance gain and 88 mW overall power consumption. The simulation and test results of the above three chips show that the three transimpedance amplifiers all have good performance, achieving remarkable low noise, high linearity and broadband respectively. That can meet the application requirements of NRZ code and high-order modulation optical fiber communication system at the same time. At present, there is still a certain gap in the design and implementation between domestic and international low noise, high linearity and broadband transimpedance amplifier. This paper not only can promote the further development of the related fields, but also has important academic value. Moreover, has important application value for the design of high performance analog integrated circuits design to our country.
学术讨论
主办单位时间地点报告人报告主题
东南大学射频与光电集成电路研究所 2013-12 东南大学李文正楼北412 罗贤亮 高速TIA设计的工艺考虑
东南大学射频与光电集成电路研究所 2014-03 东南大学李文正楼北412 姚建国 65 nm CMOS、40 Gb/s 低功耗CDR设计
东南大学射频与光电集成电路研究所 2014-05 东南大学李文正楼北412 罗贤亮 高速TIA的应用与设计
东南大学射频与光电集成电路研究所 2014-07 东南大学李文正楼北412 罗贤亮 0.13 μm BiCMOS工艺下40Gbps & 50Gbps TIA的实现
东南大学射频与光电集成电路研究所 2015-05 江宁无线谷A4-4212 罗贤亮 40 Gbaud/s光纤通信光接收机放大器设计与实现
东南大学射频与光电集成电路研究所 2015-06 江宁无线谷A4-4212 唐攀 0.13 μm BiCMOS工艺下高速ADC设计
东南大学射频与光电集成电路研究所 2015-10 东南大学李文正楼北412 宋灵建 0.13 μm BiCMOS工艺下高速DAC设计
东南大学射频与光电集成电路研究所 2016-08 江宁无线谷A4-4212 张震 0.13 μm BiCMOS激光驱动器的设计
工业和信息化部人才交流中心 2016-06 南京,明发珍珠泉大酒店 胡正明 FinFET from basic concept to what may come next
工业和信息化部人才交流中心 2016-07 深圳,科技园二期 Azad Naeemi Interconnect Architectures and modeling
工业和信息化部人才交流中心 2016-08 南京,明发珍珠泉大酒店 Christian Enz MOS Transistor Modeling and BSIN6 Parameter Extraction for Low-Voltage and Low-Power IC Design
工业和信息化部人才交流中心 2016-11 南京,江宁假日酒店 Michiel Steyaert AD and DA Convertor Design in CMOS
工业和信息化部人才交流中心 2017-08 南京,浦口创智大厦 Willy Sansen Analog Circuit Design
工业和信息化部人才交流中心 2017-09 南京,浦口创智大厦 Behzad Razavi Design of High-Performance D/A and A/D Convertor
工业和信息化部人才交流中心 2017-11 南京,浦口威尼斯酒店 Jerry Jiang High-Performance Analog Mix-Signal IC Design from Low-Power to High-Precision and to High Speed
     
学术会议
会议名称时间地点本人报告本人报告题目
ISPACS 2015 2015年11月 印度尼西亚,巴厘岛 A 40 Gb/s Fully Differential Transimpedance Amplifier in 0.13 μm SiGe BiCMOS Technology
ICCIS 2016 2016年12月 泰国,曼谷
博士生论坛 2017年05月 上海 40 GBit/s Analog Receiving Frontend for Optical Communication
     
代表作
论文名称
4x25 Gb/s 2.6 mW/Gb/s PARALLEL OPTICAL RECEIVER ANALOG FRONT-END FOR 100 Gb/s ETHERNET
A 40 Gb/s Fully Differential Transimpedance Amplifier in 0.13 μm SiGe BiCMOS Technology
A 44 Gbit/s Wide-Dynamic Range and High-Linearity Transimpedance Amplifier in 130 nm BiCMOS technolo
 
答辩委员会组成信息
姓名职称导师类别工作单位是否主席备注
陈向飞 正高 教授 博导 南京大学
乔庐峰 正高 教授 博导 解放军理工大学
王志功 正高 教授 博导 东南大学
杨春 正高 教授 博导 东南大学
樊祥宁 正高 教授 博导 东南大学
      
答辩秘书信息
姓名职称工作单位备注
唐路 副高 副教授 东南大学