With the development of the Internet, the network of innovative applications extended to all aspects of life, followed by data traffic continues to increase, while the speed requirements are getting higher and higher. In order to break through the bandwidth of the semiconductor device itself and the power consumption limit, the high-order modulation technology has good spectrum utilization efficiency as the potential application scheme of 400 Gb/s optical fiber communication standard. The high-order modulation scheme determines the characteristics of the multi-level communication signal, which requires optical fiber communication analog front-end circuit with both broadband, high linearity and low noise.
This paper is for high-order modulation format optical fiber communication system application requirements, the optical receiver in the broadband, high linearity and low noise transimpedance amplifier to start research. Firstly, the noise model of the transistor is analyzed, and the noise model of the single-ended input and the differential input transimpedance amplifier is studied. Then, according to the frequency response characteristic of the second order system, the equivalent input noise of the transimpedance amplifier is studied. Basing on BJT’s Kirk effect combined with the relationship between the current density and the temperature difference, the method of calculating the low-noise optimized bias current density of the BJT device is proposed. The formula to calculate the high frequency noise corner of the BJT transimpedance amplifier is derived in detail. Finally, the optimization design flow of broadband, high linearity and low noise
transimpedance amplifier is proposed based on synthesizing the conclusions in this work.
An ideal fully symmetrical transimpedance amplifier with the ability to handle differential input signals, and to suppress even harmonics and common mode noise, resulting in good linearity, is ideal for high linearity analog receive front-end amplifiers. The design of the 40 Gb/s low-noise fully-symmetric TIA is completed firstly in this work. However, a fully symmetrical transimpedance amplifier needs an auto-zero feedback loop to ensure its quality balance operation, in order to suppress even harmonics and common-mode noise. The conventional auto-zero feedback loop introduces extra noise at the input of the pre-transimpedance amplifier. Based on this, a cascode amplifier is used to design a fully symmetrical input stage of the low-noise fully-symmetric TIA, and a auto-zero feedback loop is created to ensure that the symmetrical transimpedance amplifier has a good balance operation, while avoiding the introduction of excess noise at the input of the fully symmetrical transimpedance amplifier. In order to form a complete low noise symmetrical TIA, a voltage amplifier stage and an output buffer stage are designed, and a formula for calculating the linear input range of the emitter degenerative resistor amplifier is deduced. The low-noise fully symmetric TIA is implemented using the Gloubal Foundries (GF) 8HP 0.13 m SiGe BiCMOS process. The chip test results show that the equivalent input noise current power spectral density is 9.6 pA/√Hz, -3dB bandwidth of 32 GHz, 2704 Ω differential transimpedance gain and 117 mW overall power consumption.
Based on the analysis of the shortcomings of the cascode symmetric transimpedance amplifiers, the 40 Gb/s high-linearity fully-symmetric TIA is designed with regulated casocde amplifier. In order to ensure a high dynamic linear input range of the high linearity symmetric TIA, the self-zero feedback loops of the high linearity symmetry TIA achieves simultaneously the function of overload compensation by drawing on and optimizing the self-zero feedback loop of the low-noise fully symmetrical TIA. Finally, the use of low-noise fully symmetrical TIA voltage amplifier and output buffer stage, constitute a complete high-linear fully symmetry TIA. The high-linearity fully-symmetry TIA in this paper is implemented using the GF 8HP process, and the chip test results show that the equivalent input noise current power spectral density is 10 pA/√Hz , -3dB bandwidth of 28 GHz, 2239 Ω differential transimpedance gain and 95 mW overall power consumption. The post-simulation indicates that the high-linearity fully symmetric TIA has a differential input current range of up to 2.6 mApp at 0.1 mA quiescent input current with less than 5% total harmonic distortion.
Single-ended input transimpedance amplifier compared to the differential input structure, lower power consumption, simpler structure, smaller parasitic capacitance, relatively easy to achieve greater bandwidth. In order to compare with a full-symmetrical structure transimpedance amplifier, and based on the study of a full-symmetric transimpedance amplifier, a novel structure of 40 Gb/s single-ended input TIA is designed. The same results were obtained using the GF 8HP process. The chip test results show that the equivalent input noise current power spectral density is 16.7 pA/
√Hz, -3dB bandwidth of 35 GHz, 1580 Ω transimpedance gain and 88 mW overall power consumption. The simulation and test results of the above three chips show that the three transimpedance amplifiers all have good performance, achieving remarkable low noise, high linearity and broadband respectively. That can meet the application requirements of NRZ code and high-order modulation optical fiber communication system at the same time. At present, there is still a certain gap in the design and implementation between domestic and international low noise, high linearity and broadband transimpedance amplifier. This paper not only can promote the further development of the related fields, but also has important academic value. Moreover, has important application value for the design of high performance analog integrated circuits design to our country.