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类型 应用研究 预答辩日期 2018-03-08
开始(开题)日期 2015-06-04 论文结束日期 2017-12-12
地点 东南大学李文正楼北412会议室 论文选题来源 非立项    论文字数 6.3 (万字)
题目 高速流水线模数转换器关键技术研究与芯片设计
主题词 模数转换器,流水线,折叠插值,采样保持放大器
摘要 随着无线通信技术的快速发展,5G通信技术已成为全球性研究的热点,峰值数据传输速率将达到10Gbit/s,需要模数转换器(ADC: Analog to Digital Converter)的转换速率达到几GS/s,同时对ADC的精度、芯片面积和功耗也提出了很高的要求。流水线型模数转换器(Pipeline ADC)和折叠插值模数转换器(Folding and Interpolating ADC, F&I ADC)是采用单通道实现高速转换器的主要类型。所以研究以流水线和折叠插值结构为基础的高速ADC具有重要的意义 本课题以Pipeline ADC和F&I ADC为研究对象,对进一步提高其转换速率和降低功耗的关键技术进行深入探讨,其主要研究内容如下: (1) 本文对Pipeline ADC的基本原理及冗余位数字矫正算法进行分析,对系统中的主要误差机制、单元电路的电路结构和设计方法进行深入研究。并对MDAC的闭环建立行为以及开关导通电阻对建立行为的影响进行解析分析。对深亚微米CMOS工艺下高速、高精度Pipeline ADC及其单元电路的设计方法进行研究。提出一种对称性栅压自举开关,通过采用新型的电路技术来克服电荷注入效应、开关管体效应、以及减小开关管栅极寄生电容。提出一种高速、低回踢噪声比较器,通过在前置放大器的输入管添加交叉耦合电容的方式,来抑制锁存器两端的电压跳变对前置放大器输入端信号的干扰,并优化了比较器的电路结构,将回踢噪声由原来的1.5mV减小到0.5mV。在此基础上在65nm CMOS工艺下设计实现了一款12bit 500MS/s高速Pipeline ADC,仿真结果表明该ADC的工作速率可达800MS/s,且在1.8V电源电压下其功耗只有225mW。 (2) 本文对高速Pipeline ADC中的关键电路模块,带有输入缓冲器的前端采样保持电路进行研究,对超级源跟随器的电路结构及其线性化技术进行深入研究。在此基础上,以超级源跟随器为基本结构,在65nm CMOS工艺下设计实现了一款带有输入缓冲器的高速、高精度采样保持电路。此电路中,超级源跟随器采用两个电压-电压负反馈环路来降低输出阻抗和提高线性度。此采样保持电路在1.5GS/s高速采样下,线性度达到了12.6bit,功耗只有27mW。 (3) 为了进一步提高Pipeline ADC的速度和降低其功耗,提出了一种负载平衡结构高速Pipeline ADC系统架构。此系统架构采用非标准级间增益级、运放和电容共享以及等比例缩小技术、无前端SHA结构来实现相邻两级共享运放闭环建立时的负载平衡,增加了ADC的速度,优化了系统的性能。同时对此方案中的共享运放输入端寄生电容和共享电容的电荷记忆效应进行了深入分析,并提出了解决方案,在此基础上在65nm CMOS工艺下设计实现了一款12bit 500MS/s 高速Pipeline ADC,其整体功耗只有147mW。 (4) 针对F&I ADC在粗细量化通道协同编码结构中,细量化通道中最低位比较器因失调等非理想因素导致的误判引起的ADC第六位的错误编码,在系统结构上进行了深入研究,提出了一种数字编码矫正电路。在此基础上,在TSMC 0.18μm CMOS工艺下实现了一款带有数字编码矫正电路的8Bit 1GS/s高速F&I ADC,测试结果表明此矫正电路对ADC第六位编码进行了矫正,提高了ADC的性能。
英文题目 RESEARCH AND DESIGN ON THE KEY TECHNIQUES OF HIGH SPEED PIPELINE ADC
英文主题词 Pipeline, Folding and Interpolating, SHA,
英文摘要 With the fast development of the wireless communication,5G wireless networks will achieve peak data rates up to 10Gbit/s, it requires Multi-GS/s high speed ADC, and the requirements of resolution, chip area and power consumption are becoming more stringent. Compare to other ADCs, Pipeline ADC and Folding and Interpolating (F&I) ADC can realize high conversion rate by one channel. Therefore, the research of high speed ADC based on Pipeline and F&I have a great significance. The Pipeline ADC and F&I ADC with single channel is studied in detail. The key techniques for further reducing the power consumption and improving the conversion speed of the two style ADCs are discussed in depth. The main research contents of this thesis are follows: (1) This dissertation analyses the basic principle and redundant digital correction of Pipeline ADC, the main error sources, modular circuits are explored deeply. The settling performance of MDAC and the effect of switch resistance on the settling time are analyzed in detail. The design method of high speed pipeline ADC and its subcircuits based on deep sub-micron CMOS technology are researched deeply. A symmetrical bootstrapped switch was proposed, which adopts novel circuit structure to suppress charge injection and body effect, reduce the gate parasitic capacitance of the MOS. A high speed and low kickback noise comparator was proposed, the kickback noise is caused by the voltage variations on the nodes that are coupled to the input. Cross-coupling capacitors are added to the input of the pre-amplifier to reduce the kickback noise. The kickback noise is reduced from 1.5mV to 0.5mV. A high speed 12bit 500MS/s Pipeline ADC with the proposed circuit techniques is realized in 65nm CMOS technology. The simulation results show that the sampling rate of this ADC is up to 800MS/s, the power consumption is 225mW from a 1.2V supply. (2) The sampling and holding circuit with input buffer is studied carefully, the super-source follower and its linearization method is studied thoroughly. On the basis of above research, a high speed and high linearity sampling and holding circuit with input buffer was designed in 65nm CMOS technology. The circuit uses two feedback loops to reduce the output impedance and improve linearity. It consumes only 27mW from a 1.2V supply. Simulation results show that 12.6 bit linearity was achieved with a 1.5GS/s input signal. (3) In order to further improve conversion rate and reduce the power consumption, a novel loading-balanced system architecture is presented in this dissertation. It uses Op-amp and capacitor sharing technique, Op-amp and capacitor scaling down technique, SHA-Less and non-standard inter-stage gain to realize loading balance of the op-amp shared by the first two stages. The proposed architecture increases the conversion rate and improves the total performance of the Pipeline ADC. The memory effect of the shared op-amp and capacitor was analyzed, and the solution was provided. And then a high speed 12bit 500MS/s Pipeline ADC is designed in a standard 65nm CMOS technology using the proposed architecture, the total power consumption of the prototype is only 147mW with a 1.2V supply voltage. (4) In high speed F&I ADC design, an important issue is the encoding error result from the fine and coarse channel joint encoding technology. The sixth bit of the ADC only uses the last comparator of the fine channel to encode, the misjudgment of this comparator caused by offset and other non-ideal factors will lead to the encoding error of the sixth bit. A digital encoding calibrated unit is presented in this paper. An 8bit 1GS/s high speed F&I ADC with this encoding calibrated unit is fabricated in 0.18μm CMOS technology with this digital encoding calibrated unit. The measurement results assess the validity of the calibration.
学术讨论
主办单位时间地点报告人报告主题
东南大学射光所 2013.05.20 无线谷A4212 王林锋 Pipeline ADC研究报告
东南大学射光所 2013.11.15 无线谷A4212 王林锋 Pipeline ADC中MDAC误差分析
东南大学射光所 2014.04.07 无线谷A4212 王林锋 Pipeline ADC数字矫正技术研究
东南大学射光所 2015.07.06 射光所 南409 陈志杰 Dater Converter and Building Blocks
东南大学射光所 2016.04.03 无线谷A4212 王林锋 TSMC系列工艺参数提取
东南大学射光所 2016.08.12 射光所 南409 黎飞 Mixed-Signal Chip Layout Design
东南大学射光所 2016.09.02 无线谷A4212 王林锋 12Bit 高速Pipeline ADC调研
东南大学射光所 2017.04.17 无线谷A4212 王林锋 面向第五代移动通信技术的ADC芯片核心技术研究
     
学术会议
会议名称时间地点本人报告本人报告题目
International Conference Machinery, Electronics and Controls Simulation 2014.08.16 北京交通大学 Design of a Gain-Boosted Cascode Amplifier with High unity-Bandwidth
2016 6th International Conference on Information Communication and Managment 2016.06.17 日本东京 东京理科大学 High Speed Pipeline ADC Using Dual-input Op-amp to Cancel Memory Effect
     
代表作
论文名称
Design of a Gain-Boosted Cascode Amplifier with High unity-Bandwidth
High Speed Pipelined ADC Uses Loading-balanced Architecture
Digital encoding calibrated unit used in 8 bit 1GS/s folding and interpolating ADC
A 10bit 200MS/s pipeline ADC using loading-balanced architecture in 1.18μm CMOS
 
答辩委员会组成信息
姓名职称导师类别工作单位是否主席备注
郑宝玉 正高 教授 博导 南京邮电大学
周建江 正高 教授 博导 南京航空航天大学
王志功 正高 教授 博导 东南大学
李文渊 正高 教授 博导 东南大学
樊祥宁 正高 教授 博导 东南大学
      
答辩秘书信息
姓名职称工作单位备注
黎飞 其他 讲师 东南大学